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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers

  • Conference proceedings
  • © 2009

Overview

Editors:
  1. Lars Svensson

    1. Department of Computer Engineering, Chalmers University of Technology, Göteborg, Sweden

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    You can also search for this editor in PubMed   Google Scholar

  2. José Monteiro

    1. INESC-ID, Lisbon, Portugal

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 5349)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: PATMOS 2008.

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Table of contents (48 papers)

  1. Front Matter

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  2. Session 1: Low-Leakage and Subthreshold Circuits

    1. Subthreshold FIR Filter Architecture for Ultra Low Power Applications

      • Biswajit Mishra, Bashir M. Al-Hashimi
      Pages 1-10

    2. Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs

      • Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici
      Pages 11-20

    3. Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

      • Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
      Pages 21-30

    4. Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction

      • Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi
      Pages 31-41

  3. Session 2: Low-Power Methods and Models

    1. Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating

      • Ashoka Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
      Pages 42-51

    2. Intelligate: Scalable Dynamic Invariant Learning for Power Reduction

      • Roni Wiener, Gila Kamhi, Moshe Y. Vardi
      Pages 52-61

    3. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption

      • Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
      Pages 62-71

    4. Power-Aware Design via Micro-architectural Link to Implementation

      • Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed
      Pages 72-81

    5. Untraditional Approach to Computer Energy Reduction

      • Vasily G. Moshnyaga
      Pages 82-92

  4. Session 3: Arithmetic and Memories

    1. Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication

      • Ioannis Kouretas, Vassilis Paliouras
      Pages 93-102

    2. Power Optimization of Parallel Multipliers in Systems with Variable Word-Length

      • Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki
      Pages 103-115

    3. A Design Space Comparison of 6T and 8T SRAM Core-Cells

      • Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel
      Pages 116-125

    4. Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization

      • Yan Li, Helmut Schneider, Florian Schnabel, Roland Thewes, Doris Schmitt-Landsiedel
      Pages 126-135

  5. Session 4: Variability and Statistical Timing

    1. Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic

      • Massimo Alioto, Gaetano Palumbo, Melita Pennisi
      Pages 136-145

    2. A Study on CMOS Time Uncertainty with Technology Scaling

      • Monica Figueiredo, Rui L. Aguiar
      Pages 146-155

    3. Static Timing Model Extraction for Combinational Circuits

      • Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann
      Pages 156-166

    4. A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA

      • Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann
      Pages 167-177

    5. Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power

      • Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah
      Pages 178-187

  6. Session 5: Synchronization and Interconnect

    1. Logic Synthesis of Handshake Components Using Structural Clustering Techniques

      • Francisco Fernández-Nogueira, Josep Carmona
      Pages 188-198
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  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Keywords

About this book

Welcome to the proceedings of PATMOS 2008, the 18th in a series of int- national workshops. PATMOS 2008 was organized by INESC-ID / IST - TU Lisbon, Portugal, with sponsorship by Cadence, IBM, Chipidea, and Tecmic, and technical co-sponsorship by the IEEE. Over the years, PATMOS has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design meth- ologies, and tools required for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2008 c- tained state-of-the-art technical contributions, three invited talks, and a special session on recon?gurable architectures. The technical program focused on t- ing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and op- mization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 41 papers presented at PATMOS. The papers were - ganized into 7 oral sessions (with a total of 31 papers) and 2 poster sessions (with a total of 10 papers). As is customary for the PATMOS workshops, full papers were required for review, and a minimum of three reviews were received per manuscript.

Editors and Affiliations

  • Department of Computer Engineering, Chalmers University of Technology, Göteborg, Sweden

    Lars Svensson

  • INESC-ID, Lisbon, Portugal

    José Monteiro

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